I have completed my BE in Electronics and Communication Engineering from Thapar University. I specialize in VLSI design and physical verification techniques, gaining extensive knowledge and practical experience in the field. My academic projects involved performing physical verification tasks, such as DRC, LVS, and ERC, using industry-standard EDA tools like Cadence Virtuoso and Synopsys IC Validator.
I am currently working as a PDK Engineer at Intel. I lead multiple projects and working closely with experienced physical verification engineers, I honed my skills in identifying and resolving layout issues and ensuring compliance with process design rules. I have a solid understanding DRC runsets and debugging skills. I am proficient in scripting languages like Python and Tcl for automating verification tasks.
I also have worked as an Application Engineer for Calibre (Physical verification Suite) at Mentor Graphics (Now Siemens). I have complete understanding of SVRF language and Calibre tools such as Designrev, Realtime, DRC, LVS, PERC, xRC etc. I am also good at writing DesignRev Scripting that helps in Calibre based automations.
I am highly detail-oriented and possess a meticulous approach to physical verification. I am well-versed in the latest advancements in process technologies, design rule manuals, and foundry-specific requirements. I have a strong analytical mindset, which allows me to quickly identify potential issues and propose effective solutions. Furthermore, my excellent communication skills enable me to collaborate effectively with cross-functional teams, including design engineers and process integration teams, to ensure a smooth verification flow.