Application

Sethupathy from India applies for Blue Card Germany

Electronics engineers

Personal data:

For personal data please contact us
with the following Applicants-ID: 16559

Profession:

Name of profession: Electronics engineers Name of latest business sector: Semiconductors/Electronics Latest occupation/title: ASIC Design Engg Latest main activities: IC Design

Education:

Completed education: master Title or Qualification: Master of Technology Specialisation: VLSI Design Additional trainings: Trainee Verification Engineer

Preferred countries:

1. Preferred country | region / city: Germany | Frankfurt am main 2. Preferred country | region / city: Denmark | 3. Preferred country | region / city: United Kingdom |

Language skills:

1. Language skills: english => excellent 2. Language skills: 3. Language skills: Tamil => excellent

Personal note /detailed application:

Work Experience:

1.APB - SPI Verification Using UVM Methodology:
APB Master Device and SPI Slave device. It supports variable length of transfer word and the core can be configured for 32 bit. It supports data latching and data transfer at both edges of clock. Responsible for verification of SPI Interface. Developed the Test environment using UVM and System Verilog. Test Plan Creation, Test environment architecture and creation, Test case coding, execution and Debug. Responsible in creating directed and random test cases and for functional and code coverage Improvement.
Tool: QuestaSim 10.2c Methodology: UVM 1.1

2. Dual Port RAM Verification:
Implemented the Dual Port Ram using Verilog HDL Independently and Architect the class based verification environment using System Verilog. Verified the RTL module using SystemVerilog. Generated functional and code coverage for the RTL verification sign off.
Tool: QuestaSim 10.2c HVL : SystemVerilog

3. FIFO verification using Verilog and System Verilog:
FIFO was verified using both Verilog and System Verilog separately. Firstly a design spec was received, and then feature extraction was carried out after that verification architecture and test plan was designed. Regression testcase was also used for higher functional coverage using system Verilog. Verified DUT with constrained random generated stimulus.
Tool: QuestaSim 10.2c HVL : SystemVerilog

Education

Academic Qualifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRM University Chennai
Master’s in VLSI Design, First Class 2012–2014
CGPA 6.12

Anna University Chennai
Bachelor of Engineering in Electronics & Communication, First Class 2008–2012
CGPA 6.58

Government Boys Hr.Sec School Trichy
HSC, Computer Science 2006–2008
Percentage 83.4%

Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.Simulation and Optimization of Double Gate (DG) FinFET Device
A Double Gate (DG) FinFET is designed in 16nm technology. Here dielectric material is used to reduce the leakage current.The Graph is compared of both using High k dielectric and Low k dielectric materials. Drain Induced Barrier Lowering (DIBL) of the device is calculated. The performance of the device is observed for using various materials.
Tool: SilvacoTCAD

2.Library Shelf Management System Using RFID
To develop an automatic library shelf management system to assist the librarians for more efficient
shelf management to find any misplaced books on the library shelf. RFID tag is used in the books
and corresponding book should be identified using RFID Reader placed in the shelf. Dropbox is
one of the promising new technology used to avoid the penalty for due date.
Tool: MS VisualBasic (Database)

Certifications

1. RTL Verification Using Verilog ( IEEE )
This module exposes to the techniques used in the industry to identify and fix design bugs that creep in while designing large VLSI IC’s using Verilog also be able to develop a verification plan from the design specifications, develop test benches for the same in Verilog and debug designs using an industry standard RTL simulator.

2.VLSI Technology ( IIT Madras )
The VLSI Technology program will focus on the development of hands on skills in designing
semiconductor devices and circuits into fabrication level. It has CMOS VLSI Design, SOC Design, Low Power VLSI Design and more. Design for test techniques to IC designs for testable designs and high yield, and use hardware description languages to design cores and standalone logic.

Technical Skills
Programming Languages:
C, C++, Perl, VHDL, Verilog, SystemVerilog, UVM Methodology.
Tools:
QuestaSim 10.2c, Xilinx 14.7 ISE, Quartus II, SilvacoTCAD.
Others:
MS Office, A+, N+, DCA, LATEX.

Inplant Training:
1.BSNL, Trichy : Understand the basics of Telecommunication Functions.
2.HCL, Chennai : Study on Hardware, Networking and System administrations.
3.Lenovo, Pondy : Training in Manufacturing Operations.

Publications:
International Journal:
International Journal of Advanced Research and Computer Science and Technology [IJARCST]
" Simulation and Performance of Double Gate FinFET " , Vol.2 Issue 2, April-June, 2014.

National Conference:
Paper Presented in NCMESP’14 " Reduction of Heating effect in a Double Gate FinFET
Device " at Velammal Engineering College, Chennai, India. Vol. 2 Issue 2, March, 2014.
Personal Details:

Languages:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
English ( Advanced Level )
Tamil ( Mother Lang )
Telugu ( Second Lang )
German {B1 Level}

Passport Details:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Passport Number : J6365679
Nationality : Indian
Passport Expiry Date : 19th April 2022
Date Of Birth : 2nd June 1991

Others:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Volunteering, MC Desk, AutoMobile, Gadgets, Yoga and Meditation.

References
1.Dr. K.Sridhar - Principal , M.A.M College Of Engineering & Technology
Email:principal@mamcet.com, Mob: (+91) 9940946286
2.Mr. M.Rajesh - Professor , M.A.M College Of Engineering & Technology
Email: rjsh.mark@gmail.com, Mob: (+91) 984388588
3.Dr. P.Aruna Priya - Professor , SRM University, Chennai.
Email: arunpriya.p@ktr.srmuniv.ac.in, Mob: (+91) 9444618186

I hereby declare that all the information is true of my knowledge

https://in.linkedin.com/in/kbsethupathy
 

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