Application

Jacob from Germany applies for Blue Card Germany

Electronics engineers

Personal data:

For personal data please contact us
with the following Applicants-ID: 16428

Profession:

Name of profession: Electronics engineers Name of latest business sector: semicondutors Latest occupation/title: asic design consultent Latest main activities: chih design consultent

Education:

Completed education: bachelor Title or Qualification: Bsc. E.E Specialisation: bacher of science in Electircal and computer engineering Additional trainings: system

Preferred countries:

1. Preferred country | region / city: Germany | hessen 2. Preferred country | region / city: Netherlands | all 3. Preferred country | region / city: Sweden | all

Language skills:

1. Language skills: english => excellent 2. Language skills: 3. Language skills: hebrew => excellent

Personal note /detailed application:

Jacob Kirschenbaim is a chip design expert. I bring 21 years of experience. I'm self driven, Team player, Diligent, Committed, Hard working, Adaptive, Thorough. I'm experienced with design stages from RTL coding through Layout. I'd developed design flows and automation as well. I'm Israeli citizen.

TECHNICAL SKILLS
Programming languages: Sverilog, perl, tcl, e, Matlab, verilog, vhdl, awk ,csh
• Cadence: Nc-sim, specman, Conformal LEC, First-Encounter, Ambit, RTL Compiler, X-route,CTS design
• Revision control: Clear-case, Synchronicity,svn,perforce • Novas: Debussy/Verdi
• Atrenta: Spyglass
• Synopsys: Dc shell, DFT compiler, DFT Max, Tetra max, Prime-time, Primetime-SI, primetime-PX, formality,
• IXIA,I-Test
• Unix,win,office
• Magma: Qurttz lec, Talus CTS
MENEGMENT SKILLS
• Project management
• Project Schedule planning
• Writing specification documents
• Working with over sea design groups
• Directors course open university • Reviewing designs
• Supervising subcontractors
• Working with test engineers
• Delivering product from spec to RTP status
WORK EXPERIENCE

Engineering A B Consulting Services Ltd. 2010 present
CEO and founder of ABCS Ltd. consulting services company. Working as a freelancer. Looking for short and mid tem contract offers. The company employs several engineers and offers design services in various fields.
Wings: dpll controller design on 14nm process.
BCM8510:10Gb mmWave phy modem. 40nm process, writing micro architecture specs. RTL coding (RS-FEC,LDPC soft slicer, tx-pre-distortion filter & Equalizer blocks, SVERILOG coding) Design flow automation development. Data base management. Synthesis flow development, running synthesis STA and LEC ,building simulation debug writing synthesis and LEC design automation scripts. Writing design connectivity checker scripts. Working Synopsys formality with and without upf. Taking Cadence Specman sp2 developer course V9.2 eRM/UVM/OVM.
QA Automation: Writing TCL scripts on I-test, IXIA to perfume automatic testing of ISIS routing protocol.
Sondrel 2007-Apr2009
Working as a consultant the for the following customers:
Siverge building STA environment TI clock tree synthesis in magma
Sondrel Helium design flow development (rtl to gds) Magma QURTZ LEC
Synopsys formality
Modem-Art (LSI) 2004-2007
Working in 3gpp development team. Designing UMTS, HSDPA and HSUPA wireless modem's SOC chips. Starting with 180u till 65nm. Developing (prel,tcl,csh,awk) scripting environment for design automation. Developing STA flow (including noise and cross talk). Developing formal verification flow for every block in the design. Developing spyglass flow (linter). Developing Debussy/Verdi flow. Maintaining ATPG flow and synthesis flow. Memory generation according to the project specifications .Working with Australia design team to integrate sverilog cores in modem art chip. Designing pad-mux (Excel to sverilog script).Writing and implementing pad mux test plane for block as a standalone and in the chip. Implementing assertions as part of test plan. Working on power aware designs. Running simulation at chip and block level in verilog and in specman e. Directed and Random testing, code coverage. Updating LEC script environment. Running Encounter LEC for new processors blocks added in new generations chips. Running LEC-verify to detect FSM dead locks and unsynchronized data crossing clock domains. Running FE(First encounter) IO placement, P&R macro placement, std cell placement ,global route, CTS design.

Tel-Aviv University 2003-2004
Research assistance in DRAPA(Defense Advanced Research Projects Agency) and Tel-Aviv university joint project. Developing a biological sensor to detect toxins in water. Working on Altera Arm base Excalibur Board. Working with FPGA development tools designing and implementing system to interface between computer optical system, and control system

TI 1998-2002
Working as a project manager. Writhing design specs, managing project schedule and resources. RTL design in VHDL & Verilog of blocks, synthesis, Chip STA, supervision on layout process. Working with design groups abroad, attending specmen course. Test vector generation and debug, leading 4 projects.
LBT6020: designing a 0.35u derivative of a DVB physical layer modem, converting chip CPU IF to I2c, functional bug fixes, managing Synthesis and scan insertion .TDL production, layout supervision.
LBT4230: DOCSIS MAC 0.35u gate array derivative. Identifying timing issues found post silicon, design re-synthesis and doing full metal spin.
Shiva: participating in project architecture team the device is integration between LBT4230 and LBT4030 adding a MIPS processor bus interface.
Bsn6040: Bluetooth point to multi point wireless SOC modem. Designing project schedule and resources. Working with subcontractors. Doing design reviews. Designing integration of Bluetooth and USB core to ARM7TDMI SOC design. Defining regression tests and modification. DFT Definitions. Solving backend issues. Patten production. Working with test engineers to receive RTP (Release To Production) status. http://focus.ti.com/pdfs/vf/wireless/bsn6040productbriefoct01.pdf
Bsn6050: ROM version of Bsn6040 (the same activities as in Bsn6040 project)
Motorola Semi Conductors 1995-1998
Working as a VLSI architecture development engineer. Developing SICA2(Single Instruction Computer Architecture) fast (2.5-8 G-flops per sec) parallel co-processor in SIMD deep pipelined architecture. Doing Architecture definitions, ALU block definition, RTL verilog coding, simulation, synthesis, core/chip integration. Issuing 5 patents in US*. MPEG2, DCT, motion estimation, implementation on SICA2.

EDUCATION
Ben-Gurion University
B.SC E.E 1991-1995
The department electrical engineering. Expertise in the field of: system's control , Signal processing and computer's Architecture
Tel-Aviv University
M.SC E.E 1996-2000
The department of system engineering Expertise in the field of computers.
PUBLICATION (US PATENTS ISSUED)*
• "Apparatus & method for matrix multiplication", 25-Nov_1997
• "A Computer System & method for performing a filter operation", 25-Nov_1997
• "Efficient multiply means & method", 25-Nov_1997
• "Signal processor & method for Fourier transformation", 25-Nov_1997
• "method and system for encoding", 25-Nov_1997
LANGUAGES
• English – speak fluently and read/write with high proficiency Hebrew – native language

 

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